The present invention relates to a semiconductor device, a manufacturing method thereof, and a manufacturing method of a semiconductor module, and particularly to a technology which is effective when applied to a semiconductor device in which a semiconductor chip is mounted on a wiring substrate, and solder balls are arranged on the lower surface of the wiring substrate, a manufacturing method thereof, and a manufacturing method of a semiconductor module using the semiconductor device.
There are numerous types of package structures of semiconductor devices, such as a ball grid array (BGA) type semiconductor device using a wiring substrate, and a quad flat package (QFP) type semiconductor device using a lead frame. Among them, in the BGA type semiconductor device (hereinafter referred to as BGA), external terminals for electrically coupling a semiconductor chip mounted within the package structure to peripheral equipment of the BGA (external equipment outside the BGA) can be arranged in a plurality of rows and columns on the lower surface (back surface or mounting surface) of the wiring substrate forming the BGA. Therefore, the BGA is more adaptable than the QFP type semiconductor device to a larger number of external terminals which increase with an increase in the functionality of a semiconductor device, while restraining an increase in the outer dimension of the semiconductor device.
As shown in, e.g., FIG. 7 of Japanese Unexamined Patent Publication No. 2006-237385 (Patent Document 1), there is a BGA type semiconductor device in which the substrate bump electrodes (external coupling terminals) of a wiring substrate (resin substrate with multilayer wiring or mounting substrate) are divided into a bump electrode group to be located at an outer peripheral portion and a bump electrode group to be located at a center portion, and disposed on the wiring substrate.
On the other hand, as shown in, e.g., FIG. 2 of Japanese Unexamined Patent Publication No. 2005-217264 (Patent Document 2), it has been known to divide the plural bumps (external terminals) of a semiconductor element (semiconductor chip) mounted on a semiconductor carrier substrate (wiring substrate) into those to be located at the peripheral edge portion of the semiconductor element and those to be located at the center portion thereof, and further dispose the plural bumps on the main surface of the semiconductor element such that the pitch of the bumps located at the center portion is higher than the pitch of the bumps located at the peripheral edge portion.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2006-237385    [Patent Document 2]    Japanese Unexamined Patent Publication No. 2005-217264